Chemical Mechanical Polishing in Silicon Processing
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The formation of oxide depends on solution and chemistry. Tungsten oxide plays a role as passivation layer to protect subsurface tungsten from dissolution or corrosion. And tungsten oxide is easy to be removed by mechanical force of abrasive since its hardness is less than pure tungsten. This process is repeated until CMP stops. Therefore, role of chemistry in particular oxidizer is important in tungsten CMP. Among many kinds of oxidizer, ferric nitrate Fe NO 3 3 - is the most successful one [ 3 , 5 ].
The schematic description of tungsten CMP mechanism is given in Figure The common and commercially available slurry for tungsten CMP has alumina-base and silica-base abrasives [ 3 , 5 ]. It requires superior planarity and extremely accurate uniformity control. For this purpose, alumina abrasive showed better planarity and selectivity performance.
Hence its utilization for bulk tungsten CMP is commonly adopted in advanced device manufacturing. Alumina abrasive has been synthesized by alum process and calcination [ 18 ]. For CMP application, alpha-alumina abrasive is commonly used. Hardness of alumina abrasive is much higher than tungsten and tungsten oxide, therefore it is easy to make scratch defect on the surface.
Moreover, due to the surface charge difference between alumina and tungsten at acidic region, attractive force retains alumina abrasive on the wafer surface. Recently, composite alumina abrasive with polymeric material has been introduced in the industry due to defect concern at advanced node semiconductor [ 38 ]. Silica base slurry utilization on tungsten CMP is usually for non-selective CMP purpose polishing both tungsten and dielectric material because its selectivity with oxide is not as high as alumina abrasive slurry.
Tungsten CMP is driven by chemical effect more than mechanical abrasion, removal rate strongly depends on chemical components oxidizer, surfactant, and stabilizer and activation condition for example, process temperature [ 39 , 40 , 41 ]. Therefore adequate combinations among them are essential to provide desired CMP performances. Although removal rate is linearly increasing with abrasive concentration in the slurry, loading effect very low removal rate or non-linear removal rate behavior at the early stage of CMP is more significant in tungsten CMP than dielectric CMP.
Yttrium, ceria, zirconium and composite abrasives have been tried and under development for tungsten CMP applications [ 3 ]. Copper is introduced in semiconductor manufacturing for metal interconnection application mids and now it is standard metal for back end of the line interconnection [ 2 , 3 , 4 , 10 ]. Accordingly, CMP for copper has been highlighted due to its process challenges. Chemical reaction from slurry produces oxidized copper and abrasive particle removes oxidized copper.
The major components of copper CMP slurry are abrasive, oxidizer, inhibitor, surfactant and chelating agent. The challenges of copper CMP are scratch defects and copper corrosion. Corrosion is mostly induced by chemical in the slurry and most of scratch defects are driven by abrasive particle. In particular, hardness of copper is lower than most abrasive particles. Therefore, smaller size of abrasive with spherical shape and less abrasive content are favorable to the slurry formulation.
The common copper CMP abrasives are alumina and colloidal silica [ 3 , 10 ]. The copper removal rate and CMP performances are sensitively influenced by chemistries and components in slurry in conjunction with silica abrasive characteristics. Most of copper CMP slurry researches have focused on chemistry perspective instead of abrasives. One of the most important requirements of CMP process in semiconductor application is scratch defect reduction, which has mentioned in this chapter several times.
For abrasive perspective, smaller size abrasive particle is favorable for scratch defect. Therefore, recent abrasive technology has focused on nano-sized abrasive synthesis with minimized agglomeration. For dielectric CMP, nano-sized cerium hydroxide or ultrafine cerium hydroxide or nano-ceria abrasive slurry has been introduced due to its potential scratch defect reduction [ 33 , 34 , 42 , 43 ]. The synthesis procedure of nano-sized cerium hydroxide abrasive is given in Figure Synthesis of nano-sized cerium hydroxide abrasive reprinted from Ref.
Transmission electron microscope image of calcined ceria abrasive and nano-sized abrasive is compared in Figure 14 [ 44 ]. However, CMP mechanism of nano-sized cerium hydroxide abrasive is not clearly understood yet. Kim proposed particle coverage model on the wafer as material removal mechanism with nano-sized cerium hydroxide abrasive [ 43 ]. In order to apply nano-sized cerium hydroxide abrasive for dielectric CMP, role of chemistry to enhance removal rate with selectivity control needs to be further explored.
TEM images of a calcined ceria abrasive and 2 nano-sized cerium hydroxide abrasive reprinted by permission from Ref. Composite abrasive has drawn attention to the semiconductor industry recently. Each abrasive has its own unique properties. Some of them are very attractive and some of them are not good for desired CMP performances. Tries to combine advantages only from different abrasives have triggered ceria-silica composite abrasive development [ 45 , 46 , 47 , 48 ]. Researchers have paid attention to ceria-coated silica as next generation CMP slurry abrasive.
They prepared tetraethylorthosilicate and ammonia as raw materials, and composite nanoparticles are synthesized through precipitation procedure. In their study, X-ray diffraction confirms face centered cubic CeO 2 nanoparticle encapsulate core silica. Scanning electron microscope SEM shows uniformly distributed particles with spherical shape. Transmission electron microscope TEM directly shows evidence of homogenous nucleation of ceria particles and heterogeneous nucleation of silica particle with uniform, distinctive and crystalline ceria shell.
With ceria-coated silica composite abrasive, higher removal rate than pure silica abrasive and comparable surface roughness is demonstrated on glass substrate CMP. The advantage of mesoporous silica is its significant elastic recovery ability combined with ductile behavior. It uses vinyltrimethoxysilane VTMS as silica source and cetyltrimethylammonium bromide as structure directing agent.
Well defined spherical shape abrasives are successfully achieved and it shows clearly core-shell structure. The thickness of mesoporous silica shell is controlled by VTMS amount during synthesis. With this abrasive, higher removal rate of thermal silicon dioxide film and lower surface roughness are exhibited. Polymeric composite has drawn attention to CMP society due to its potential scratch defect reduction.
The core abrasive is spherical polystyrene PS and ceria is selected as shell abrasive [ 49 ]. The mechanism of low scratch and minimize wafer damage is cushion effect of soft polymer core abrasive. Nano-sized ceria abrasive is already used in the semiconductor manufacturing. Ceria-silica or silica-silica composite abrasive is still under development stage although several unique synthesizes are suggested and demonstrate promising CMP data. Most of literatures with composite abrasive focus on material removal rate and surface quality. However, CMP application needs more performances.
In order to be utilized in the industry, composite abrasives have to avoid agglomeration, need to robust abrasive stability, require optimized chemistry, and more CMP performances such as selectivity and defectivity must be fulfilled. New materials CMP has emerged along with new device introduction and device node shrinkage, from ultra-soft materials such as porous low-k and photoresist to highly non-reactive metal such as ruthenium Ru [ 3 , 4 , 5 , 50 , 51 ].
Ultra-soft material CMP needs very soft abrasive or even abrasive-free slurry development [ 5 ]. Ru is little chemical reactive metal with high hardness. And it relies more on mechanical force to remove Ru layer than chemical dissolution. Moreover, RuO 4 , which can be produced by slurry chemistry, is toxical gas [ 50 , 51 ]. More difficulties on these materials are not only target material CMP but also neighboring materials CMP for proper selectivity. Most of new materials CMP slurry is based on silica abrasive and chemistry optimization has been underscored.
However, it still has a lot of opportunities to develop abrasives as well. Carbon based materials either carbon nanotube or graphene have drawn intense interests to the semiconductor industry for a long time. For CMP perspective, carbon-based material polishing, which has been rarely reported, is big challenge to abrasive development due to its high hardness. The role of abrasive in CMP application is to obtain enough material removal rate, desired selectivity and low defect residual particle and scratch performance. In addition to develop advanced abrasive material and synthesis, abrasive size distribution and dispersive ability in the solution has been developed to control large particle count.
Particle size distribution is raw abrasive material nature resulting from synthesis, however, slurry distribution system and filtration can control large particles and agglomeration from the slurry without CMP performance degradation. In high volume semiconductor manufacturing fab, slurry distribution system is considered as infrastructure instead of equipment [ 18 , 55 ]. It consists of 1 slurry drum, 2 agitation of drum drum tumbling , 3 slurry blending and dispense, 4 daytank or standby tank with stirrer, 5 looping to tools.
Figure 16 shows simplified distribution system. Slurry is being circulated in the loop until it is used for CMP. Abrasive agglomeration is induced by shear stress, temperature change and chemistry variation if proper filtration is not implemented [ 56 ]. The location of filters from slurry distribution system is selected carefully. More filtration drops slurry flow pressure quickly by filter itself. Very fine filter will removes most abrasives, which results in low removal rate.
Different slurry needs different type of filter and filtration at different locations; however global loop filtration and point of use POU filtration at polishing equipment are quite standard [ 18 , 56 , 57 ]. Colloidal silica abrasive agglomeration is more sensitive to shear stress than ceria abrasive.
The most important challenge of filtration is plugging by abrasives. Three plugging mechanisms in filtration are well known, which are cake formation, gradual plugging, and complete plugging [ 58 ]. Cake formation is driven by particles build up on the filter surface, gradual plugging is induced by particles building up on the pore, and compete plugging indicates pore blocking by particles. Depending on particle size, deformability, and agglomeration, filtration procedure can be optimized. It has multi-layers of fibrous media and there is retention gradient along with flow direction. Commonly, large particles are captured first at outer layer and small particles are retained at inner layer.
However, more advanced filter and filtration researches are reported recently. Nano-fiber based advanced filter to remove large abrasive as well as avoid agglomeration is reported. In addition to filtration, dispersant in the slurry prevents abrasive from agglomeration. For high abrasive content slurry case, abrasive particles are easy to sediment and agglomerate by particle charge interaction. Along with slurry abrasive development, advanced filter development and prevention of sediment of abrasive are required in slurry preparation. Slurry delivery facilities in semiconductor manufacturing fab.
This chapter reviews abrasives for CMP applications in semiconductor manufacturing. It includes abrasive types, abrasive synthesis, CMP mechanism and role of abrasives, and opportunities of new abrasive developments. Semiconductor business increases explosively and various semiconductor structures with high performance have been developed according to market requirement.
In order to achieve mature semiconductor manufacturing, CMP process development is critical and abrasives in slurry play a pivotal role in determining CMP performances. The most common abrasive in dielectric CMP is either silica-based or ceria-based one. For metal CMP tungsten and copper , silica is the most popular abrasive. Advanced synthesis for silica or ceria abrasives, new abrasive materials, and composite abrasives have studied for high performance CMP and new material CMP.
Furthermore, the control of slurry abrasive in the looping is emphasized. Advanced filtration is critical to maintain abrasive size distribution. The key of each application is noble abrasive development with proper chemistries. Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution 3. Help us write another book on this subject and reach those readers. Login to your personal dashboard for more detailed statistics on your publications.
Edited by Anna Rudawska. We are IntechOpen, the world's leading publisher of Open Access books. Built by scientists, for scientists. Our readership spans scientists, professors, researchers, librarians, and students, as well as business professionals. Downloaded: Orbital CMP uses relative velocity values that are similar to the speeds of other CMP tools, but with a small tool footprint. Generally speaking, the processes are similar. Additionally, high relative velocity values can be achieved at high orbital speeds with no adverse effect on removal rate uniformity. Thus, with systems such as the one shown in Fig.
These trends are shown in Fig. Orbital pad motion also enables slurry to be delivered directly to the surface of the wafer, which improves slurry distribution [ However, grooves must be formed in the pads to ensure uniform slurry distribution. For production convenience, the grooves are Cartesian. The ensuing motion of the grooves, especially of the groove intersections, against the wafer causes a spirographic pattern to form if compound motion is not added.
Schematic diagram of a third-generation, orbital CMP head. A wide retaining ring is used to ensure the pad remains compressed during the entire polishing cycle. Controlling the pressure difference between the pad and the retaining ring optimizes uniformity in the edge exclusion region.
The padbacker assembly is held in place by a quick release buckle; pad assemblies 0. Normalized planarization as a function of process. Production orbital polishers have four independent polish heads that can be randomly accessed for either single pad processing or multiple processing steps. Planarization capability on these tools has been demonstrated to be significantly better than that on first- and second-generation polishers. The rapid change capability of individual polish head pads minimizes the down time associated with conventional tools during pad change. Pad Feed Web Polishers A polish technology that is just emerging from development by several CMP capital equipment suppliers is the pad feed polisher.
This equipment is based on some fairly recently developed polish pad rolls. These polish pads are in a roll similar to mm camera film. The pad is fed out to the wafer polish table, a wafer is polished, the pad is conditioned, the pad is incremented forward, and then the next wafer is polished.
Successful polishing with such a methodology strongly relies on the pad characteristics being consistent from beginning to end. This method is particularly useful for pads with very consistent first polishes, but whose characteristics degrade rapidly with subsequent wafer polishes. While this tool design has no significant polish performance or polish mechanism improvements over non-pad-feed polishers, it does have a strong advantage: tool utilization. With almost all polishers being used today except this one, the polisher must be turned off once a day to remove the worn polish pads, place new polish pads on the tools, and qualify the tool before restarting production.
With a continuous-feed pad of adequate length, fabs can continue to process wafers without pad changes for up to a week. This could significantly improve CMP tool utilization by the fabs. Carriers Aside from the basic approach to polishing, the most critical component of a CMP tool is the wafer carrier. As with CMP tools, wafer carriers have evolved from roots in lens grinding and in the silicon wafer polishing industries to meet requirements specific to polishing silicon-based integrated circuits. The basic function of the wafer carrier is to hold the wafer in place while the wafer is polished.
A more detailed description of the basic function of a carrier is given following a summary of the processing issues being addressed by carrier designers. On many carriers, the wafer is placed against a carrier film that is used to compensate for small amounts of wafer bow, tilt, or warp. Finally, at the completion of the polish cycle, the carrier must release the wafer upon command. In CMP, carriers must meet two additional requirements.
First, polished wafers must be flat to within a predetermined specification across the wafer, but excluding the so-called edge exclusion region. The edge exclusion region is an annular region of the wafer at the wafer edge where the removal rate deviates significantly from that of the bulk of the wafer.
Ideally, the width of this region is zero, and carrier design engineers continue to improve carriers to reduce the edge exclusion region to zero. Figure 5 shows the effect of reducing the edge exclusion and the clear need for minimizing wasted real estate on a wafer. In , typical processes were quoted with measurements made at edge exclusions of 5 to 7mm.
Wafer Polishing Process, Polishing Pads and Diamond Liquid Slurry
In specifications including 3-mm edge exclusion became the standard. It is anticipated that by the year near zero edge exclusion will be the norm. The edge effect arises from the interaction of the carrier with the pad. The dynamic action during polishing causes the pad to be compressed as the platen rotates. Plot of the percentage of the maximum number of chips that can be obtained from a mm wafer as a function of edge exclusion for several representative chip sizes.
For small chips, the sensitivity is essentially linear, while for large chips there are plateaus in which further decreasing the edge exclusion has no impact on the percentage of possible yield. Physical contact is maintained, but the pressure on the wafer in this region is much less than it is in the adjacent regions.
Consequently, this narrow, annular region experiences a correspondingly lower removal rate. The net effect of this process is known as the so-called edge. This effect is shown in the diameter scan in Fig. Figure 7 shows an expanded view of the edge effect. Baker  derived an elegant description of the edge effect based on the mechanics of the pad and of the wafer.
This relationship indicates that there is a weak dependence of the peak on the material parameters of the pad. Wang et al. Both approaches agree that hard pads give better profiles in the edge exclusion region, but neither model fully addresses the overall interaction of all key process parameters.
Wang and coworkers went on to show that the carrier film plays an important role with both the magnitude and location of the edge effect. They showed that thin, hard pads give the best edge exclusion [ Diameter scan of thickness minus the mean of a wafer that was polished using a first-generation rotational polisher. Radial scan of film thickness at the edge of a wafer after removing A of PETEOS on a wafer that was polished using a first-generation rotational polisher.
With respect to the edge exclusion, orbital tools differ from other C M P tools because during use virtually the entire pad is in compression. In contrast, rotational tools periodically compress and then release the pad as it passes under the carrier and rotates around the tool. Very little data is publicly available regarding the fundamental properties of pads, so the significance of this difference between tool types is not well understood. The second additional requirement of CMP carriers is that they must allow the tool to polish a broad range of films with varying amounts of film stress.
Film stress causes the wafer to deform, altering the pressure distribution across the wafer during CMP. These pressure variations cause characteristically fast or slow polishing across the wafer. This picture is further complicated by the time dependence of this stress during the course of the polish cycle.
Depending on deposition tool parameters, the deposited films may have lattice constants that differ from those of the films on which they are deposited. This mismatch induces stress in the wafer. This stress can be either tensile or compressive, and can have a significant impact on C M P . A tensile film causes the edges of the wafer to bow up. When pressed against a polish pad such a film would exhibit a center slow polish profile i. A compressive film causes a center fast process.
In other cases, stress arises because the preceding processing steps were poorly optimized from an overall integration perspective, and sometimes the particular stress distribution is simply a result of a prior process being locked in for manufacturing purposes. A number of approaches have been developed to accommodate film stress. The use of back pressure enables one to deal with modest bowing and for dealing with variable process conditions e.
For more severe situations, the carrier face is built with a small amount of curvature. Typically, the center of the carrier extends out from the plane of the periphery by 5 to 20 pm. Once the appropriate amount of curvature has been identified, small amounts of back pressure are then used to fine-tune the process. A variety of other methods have also been published, including several from the patent literature. These other methods involve introducing a spatially variable amount of back pressure to the wafer, for example, by including concentric rings within the carrier head that can be pressurized to different pressures .
On a so-called gimbaled carrier, the down force was applied to a central point on a plate behind the wafer, and it was assumed that the applied force was transferred through the wafer backing plate to be distributed uniformly across the wafer. Lateral motion of the pad then caused a torque to be applied to the carrier. To compensate for this rotation, a gimbal was built into the carrier at the point where the down force was applied.
The nonuniformity is more precisely called the within-wafer nonuniformity WIWNU and is defined by the standard deviation of a set of film thickness measurements on a wafer divided by the mean of that set.
Smaller numbers denote better process control. Better performance was limited in part by the manner in which the carrier held the wafer during polish. Even in the absence of the edge effect, several other issues limited the ability of these carriers to produce very flat wafers. First, the application of pressure to the center of the wafer, in spite of the rigid structure of the 2 EQUIPMENT 21 carrier backing plate, caused wafers to polish center fast.
Second, poor slurry flow to the center of the wafer caused wafers to polish center slow. These two factors partially offset one another with slurry distribution believed to be the stronger of the two. Only in the late s has the impact of slurry flow on CMP received any attention, and it is likely to play a much greater role in CMP as it becomes better understood [ 2 5 , 2 6 ]. Process parameters, of course, also play a role as well as the film stress in the wafers being polished. There are two basic methods used to address these effects: back pressure and the use of curved carriers. Back pressure consists of increasing the pressure applied to the wafer via a port behind the wafer plate.
The use of back pressure is preferred since it is readily adjusted to compensate for a broad spectrum of issues. Adequate performance is attainable in most cases. However, in cases of extreme film stress, it is often necessary to use a curved carrier. Such carriers have a wafer plate with a small amount of curvature built into them. The maximum deflection is in the center of the carrier, and is typically about 5 to 15 pm. FLOATING Experience with the gimbal-styled carriers led designers to rethink the purpose of a carrier as well as the approach to designing better carriers.
Two definitions emerged. First, the purpose of a carrier was to hold a wafer as flat as possible so that a uniform thickness of material could be removed from the wafer surface to eliminate surface roughness. This definition implies that removal is referenced to the pre-CMP surface i. This definition is essentially the one used by the raw wafer polishing industry. Any imperfections in the surface of the wafer must be accommodated by the flexibility in the polish pad. This definition does not take into consideration the potato chip shape of partially processed wafers with the topology of integrated circuit designs on them.
The second definition of the purpose of a carrier was to remove the overburden of material above a surface above the device plane. For present purposes, we define the device level as the boundary between the material one wishes to remove and the material one wants to keep. It is not necessarily planar, and it moves up with each layer. For oxide CMP, this layer lies within the topmost film layer. For metal CMP, this surface is defined by the topmost surface of the dielectric into which lines and vias are etched for a damascene process. This definition must accommodate a wafer with a modest amount of bow, tilt, warp, and total thickness variation.
The demands placed on carrier designers of such a definition are much greater than they are for designers addressing the first definition. Thus, the goal in initial carrier improvement was to develop a means to apply more uniform pressure between the wafer and the pad. Significant improvement in carrier performance resulted from the use of pneumatic or hydraulic pressure. The basic concept underlying the design improvement is the presence of a cavity into which pneumatic or hydraulic pressure is applied, and a flexible membrane that couples the pressure to the wafer.
This concept is shown in a simplified manner in Fig. Although the flexible membrane confines the pressure, its primary purpose is to respond homogeneously to the pneumatic pressure. In so doing it applies pressure uniformly across the wafer. There are other similar inventions involving the use of membranes to assist in applying pressure uniformly dating from the same time [ This approach has proved to be so successful that it has spawned a cottage industry of carrier designs based on the use of hydrostatic pressure.
With some of these inventions a backing plate is present, with others  FIG. Wafer carrier with a floating carrier plate. Pneumatic pressure is applied through an inlet resulting in hydrostatic pressure directly against the wafer. There is not necessarily any independent retaining ring control. In one invention, the pressure applied to the retaining ring is adjusted separately from that of the carrier . Another carrier design uses concentric pistons with independent pressure control .
A subsequent invention involves the use of a wear ring with independent pressure control to minimize the edge effect, and the use of a lip seal to allow limited vertical wafer motion independently of the retaining ring . Another invention using multiple bellows achieves the same end: independent control of the pressure on the retaining ring as on the wafer .
All of these approaches are intended to address global planarization issues. We close this section with a brief note about an alternative approach that focuses on achieving planarization at the die level. The distributed polish head , extends the concept of hydrostatic pressure by integrating polish blocks in the carrier design to minimize the locally the spatial variation in the polish.
As shown in Fig. Control of the fluid pressure in these bearings regulates the pressure distribution that the wafer experiences. These channels are controlled in groups. A central fluid bearing is larger than the others, and contributes most to controlling the removal rate in the center of the wafer. Platens The platens on which wafers are polished have also evolved over time. Traditional polishing, as is done on first- and second-generation CMP tools, is done on a hard platen.
The reason for a hard platen, of course, is to present as close to absolutely flat a surface as possible against which the wafer is pressed. Ideally, platens rotate perfectly. In practice, however, there is a small amount of run-out, or wobble, which limits the ability of the tool to polish films uniformly, especially at high rotation speeds.
Although typically not thought of as a platform for more than presenting a flat surface, platens are being exploited in several ways to enhance overall CMP performance. Included in these approaches are temperature control, slurry delivery routing, and pressure control. First, the chemical aspect of CMP is temperature-dependent. This is especially the case for most metal CMP processes and for exothermic processes such as silicon polishing.
Abrasive for Chemical Mechanical Polishing
Increasing the temperature increases the chemical reaction rate and hence the removal rate. However, other effects temper the benefits of increasing the temperature. Since the glass transition temperature for polish pad materials is approximately 65"C, increasing the temperature causes the material in currently used polish pads to soften.
This causes the pads to deform more, so uniformity improves and planarity deteriorates. On the other hand, decreasing the pad temperature causes the pad to stiffen, which can be used advantageously to improve oxide CMP planarization performance. A stiffer pad deforms less, so planarization improves, especially on a feature scale . On a wafer scale, however, excessive pad stiffness can lead to very good planarization, but with excessive material removal in some areas.
Second, friction during CMP generates heat that can affect the reaction kinetics as well as soften the polish pad. The rate of heat removal increases with increasing slurry flow, so one reason there is a limit on reducing the slurry flow rate is the effect it has on polish temperature. In addition, some processes such as silicon polishing are exothermic, so there is even more heat to remove than with either metal or oxide CMP. Temperature control is accomplished in one of three general ways. One method is by controlling the temperature of the platen, usually by means of an integral channel in the platen through which temperature-controlled heat transfer fluid flows.
Second, the temperature of the slurry itself can be regulated prior to being dispensed onto the platen. Finally, a means of heating the backside of the wafer can be built into the carrier [42,43]. Slurry injection through the pad is particularly important with high-speed processes, where the removal rate is limited by pad absorbency and slurry transportation, The orbital platform sold by SpeedFam-IPEC is unique in that the pad is not rigid.
The platen consists of a thin disk of stainless steel on which a 4. The pad backer has grooves in it to allow greater flexibility. It also contains holes between the grooves that are aligned with holes in the underlying backing plate through which slurry is delivered. By delivering slurry directly to the pad-wafer interface, process engineers have a great deal of latitude in controlling slurry distribution across the wafer during polish.
In other words, they can design processes that do not suffer the limitations of pH or oxidizer concentration gradients across the wafer. Oxide and metal CMP processes are very different, so it is useful not only to be able to inject slurry directly to the wafer surface, but also to control where on the wafer the slurry is delivered. Pad Conditioning Pad conditioning is the process of revitalizing a polish pad to produce reproducible, consistent results [44,45].
Polymer is abraded from the surface of the pad. Slurry particle agglomeration can take place in the slurry in which abrasive particles and colloids coalesce to form extended particles. Any and all of these particles can become attached to the pad. As the surface of the pad accumulates more and more particles, the surface glazes and becomes smoother and less abrasive. Consequently, the removal rate declines. Also, as the pad becomes glazed it becomes smoother, which causes a decline in the ability of the polish pad to distribute slurry under the wafer.
At present there is considerable debate as to whether CMP takes place in a contact regime or in a lubrication regime. It is likely that resolution of this issue will be necessary to establish what fundamental limits there are on slurry flow, as well as how these limits affect pad conditioning. Some work has been done to correlate oxide CMP performance with pad properties . This work indicated that the specific gravity of the pads and the cross-linking densities affect polish performance.
Other work has been done to correlate CMP performance with slurry composition . The porous structure of the pad shown  in Fig. If one considers the action of pad conditioning to clear the pores, then some study of polishing, that is, clogging of the pores may shed light on the mechanisms of pad conditioning. Figure 11 shows  a log-log plot of removal rate as a function of total polish time on a pad. The straight line indicates a power law governs the variation in the removal rate, that is, where RR, is the initial removal rate and y is a measure of how rapidly the removal rate diminishes in the absence of pad conditioning.
For the data shown in Fig. An indication of the improvement in performance that this value of y represents is that a log-log plot of the data shown in Fig. Pad conditioning serves to reverse the pore-clogging process, and there are two general approaches that seek to apply any of several pad-conditioning methods. One approach consists of concurrent pad conditioning. Scanning electron micrograph SEM of a polish pad. The second approach involves sequential pad conditioning in which the pad is conditioned prior to polishing each wafer.
Several methods have been developed for conditioning pads.
Chemical mechanical polishing in silicon processing
The most common uses a diamond-coated disk that is pressed into the pad and rotated about its center axis as it moves radially across the pad. Conditioning disks are made of diamond-impregnated nickel or of a nonmetallic substrate on which a diamond grit has been epitaxially bonded [SO]. The diamond grit scratches the surface of the pad, causing some particles to be dislodged. Once dislodged, they can be swept from the surface of the pad. Even if the particles are not removed from the pad a likely scenario given the gluelike nature of silica , the grooves in the pad stemming from the action of the conditioner enable slurry transport to take place.
Additionally, unless the pressure is exceptionally light, pieces of the pad itself are abraded as well. Depending on the pressure applied, the application of excessive pressure can lead to premature pad failure. Plot of instantaneous removal rate without pad conditioning vs polish time using Klebosol slurry and a Freudenberg FX9 polish pad. This figure shows the removal rate as a function of wafer number. During the polishing of the first 43 wafers there was no pad conditioning, and the removal rate declined rapidly.
Once concurrent pad conditioning was initiated, the removal rate exceeded its initial rate and remained steady. Other methods of pad conditioning, such as the use of high-pressure deionized water [Sl] and acoustic energy  have been proposed for applications requiring aggressive pad conditioning.
These methods show promise, but to date have not seen widespread use. Other CMP applications do not require such aggressive pad conditioning. For example, pad conditioning for tungsten plug CMP is done with a conditioner. Pad conditioning is also used to shape the pad during polishing to improve uniformity. Figure 13 shows a plot of the pad thickness after polishing wafers on a rotational platform. The bar in the figure indicates the location of the wafer during polish.
The effect of pad conditioning on shaping the pad is evident. For the process shown in the figure, the pad was curved to enhance the removal rate in the center of the wafer. Pad shaping is accomplished by adjusting the amount of time the pad conditioner spends at each radius . Other control parameters process engineers may use include the down force exerted by the pad conditioner and the rotation speed of the conditioning disk. Plot of removal rate as a function of wafer number showing the effect of pad conditioning. Data c. Pad profile after polishing wafers.
The bar denotes the normal position of the wafer during polish. This result is achieved by increasing the pressure in regions where a lower removal rate is desired, or by increasing the dwell time in these regions. Care must be taken to condition the pad uniformly. Poorly chosen conditioning parameters can cause portions of the pad to be highly overconditioned while other portions are not conditioned at all.
Alternative means of addressing the issue of nonuniformity due to nonuniform pad wear include the use of a platen with a carefully designed raised region under the path of the carrier , and the use of polish pads with regions of less compressibility under the wafer [SS]. The original tools met functionality requirements most of the time! The need for a reliable source of slurry during C M P stimulated the growth of a whole industry of bulk chemical distribution BCD systems. An extended discussion of BCD systems is beyond the scope of this work, but a few words are in order.
Slurry distribution systems vary in sophistication from the simple laboratory system consisting of little more than a barrel of slurry and a pump to sophisticated delivery systems designed to supply slurry to tens of CMP tools in a high-volume production environment . Suppliers of second- and third-generation tools are integrating cleaners and metrology equipment into CMP tools to improve efficiency, and to ease the integration into the main fab. In addition, such integration enhances the overall quality of the polished wafers because the CMP and cleaning processes can be optimized together in a single dry-wafer-out DWO process.
Early on it was recognized that cleaning processes most commonly, brush cleaners were essential for enabling CMP to be used. Even then, CMP processing was typically done in an isolated area well away from the rest of the fab. Post-CMP cleaning specifications are becoming ever more stringent. For an extended discussion of post-CMP cleaning, refer to Chapter 7.
The Gotkis rules are: 1. Never allow slurry to dry on wafers. Strong bonds are formed when slurry dries, making the removal of the slurry nearly impossible. The bonds are formed between the abrasive, the abraded pad, the abraded material, and the wafer. The bond strength is such that even supplementary cleaning steps are insufficient to remove the slurry. Include a precleaning andlor bujing step as an integral part of the polish recipe.
Rinse and buff immediately afer the bulk C M P step. Rinsing removes the residual slurry and the polishing by-products including abraded film from the wafer, abraded polish pad material, and agglomerated slurry. Buffing removes most of the particles that are adhering to the surface as well as many mechanically embedded particles. Decreasing particle size means increased effort required to remove it.
This rule arises from the smaller interaction cross sections for collision and momentum transfer. Both of these factors lead to redeposition being a major source of small particles. Since mechanical action requires increasing amounts of work, chemical dissolution is more effective at removing small particles than is mechanical action.
Minimize surface roughness to limit sites at which particles can adhere. This point is especially true for small particles and removal methods exploiting mechanical means. A rough surface can shield small particles from momentum transferal from brushes. Avoid C M P chemistry that involves multicharged cations. Such chemicals compress the double charge layer and activate slurry agglomeration and process defectivity.
Use any and all options for post-CMP cleaning. Keep particles from adhering more strongly than they already are, and remove them as quickly as possible. Once they are removed they must be transported away from the wafer surface as quickly and efficiently as possible to minimize redeposition. The drawback to the use of multiple mechanisms of cleaning to produce cleaner wafers is a decrease in the reliability of the tool due to increased system complexity.
A related factor is an increase in the overall COO due to an increased footprint. Furthermore, cleaning methods that use a lot of consumables e. Although performance is the dominant factor driving post-CMP cleaning, the efficiency of any given method of removing particles is also very important. Further improvements to the CMP tool that do not also reduce the time to clean wafers will not increase the overall throughput. However, of these the vast majority are double-sided brush scrubbers. An example is the OnTrak cleaner shown in Fig.
Brush configurations consist of either a series of rollers [SS] or opposing pancake scrubbers. Cross-sectional views of post-CMP cleaning using double-sided roller brushes. The two brushes roll in opposite directions to keep the wafer pressed against two rollers. The rollers are used to rotate the wafer and are withdrawn to allow the wafer to pass once the wafer is clean: a a single-brush configuration and b a multiple-brush configuration.
However, H F is well known for its safety issues, so there is considerable impetus to develop alternate PCMP cleaning solutions that provide comparable or better performance than dilute HF. Double-sided brush scrubbing followed by a spin-rinse-dry step dominates the industry. An example of a double-sided brush scrubber is shown schematically in Fig. The rollers keep the wafer positioned and rotating while the brushes clean debris from both the front and back sides of the wafer.
The cleaning solution is delivered through the bristles themselves. Typically, the bristles are porous so that fresh solution can be delivered directly to the wafer and minimal amounts of debris accumulate on the brush. Increasing the down force increases the particle removal efficiency up FIG. Schematic of double-sided brush cleaner using pancake brushes. Figure 14 shows a roller-based post-CMP cleaning method.
With this technique wafers are transported through the cleaning region while the brush scrubs the top surface of the wafer. Alternative methods, such as megasonic cleaning, have been proposed as noncontact cleaning methods. Megasonics is a term used loosely to describe all acoustic based methods of particle removal.
Ultrasonic excitation in the 20 to kHz regime or megasonic agitation in the 0. Some preliminary work has also been done involving nanosecond pulses of laser light to very rapidly heat localized regions of the wafer causing an abrupt expansion wave to expel particles from the surface of the wafer. This method is intriguing from the point of view of using very small amounts of consumable materials.
However, from a CMP tool point of view there are concerns about the size of a cleaner based on pulses of laser light using existing laser technology, as well as about throughput issues. An alternative approach is the use of megasonic energy . This cleaner uses a quartz arm to which a megasonic transducer has been affixed. Schematic representation of the Verteq Goldfinger that uses acoustic energy. The quartz arm contains a megasonic transducer that sweeps acoustic energy across the wafer while it rotates.
This meniscus acts as an acoustic coupler and waveguide between the wafer and the transducer. Limited results have been reported to date, but those that have been reported have been encouraging. By incorporating these measurement systems into run-to-run control systems, closed-loop control is being used to tighten process specifications [63,64]. These systems also address the impact on throughput due to off-line measurements during process qualification following a pad change or other PM action. It can take as long as 2 hr to confirm that the tool is running properly.
In addition, while waiting for the results from the monitor wafers, the tool is idle, and the pad properties can change. Integrated metrology in CMP is therefore increasing in importance from a strong desire to an essential component of CMP tools. There are two major methodologies in use for in-line metrology: wet and dry. Dry measurements are done in a similar manner, except that the wafers are measured after going through an integrated cleaner, and the measurements are done in air.
The advantages of measuring wet wafers are that the delay in obtaining measurements is minimized, and essentially no contamination issues arise. Since dry measurements are done following post-CMP cleaning, there is a delay of a couple of minutes between the time a wafer is polished and the time it is measured.
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In principle, with wet in-line metrology, the next wafer to be polished can benefit from a process modification due to the wafer just being measured. In-line measurements are ideal for use as statistical process control tools and controlling relatively slow and predictable changes in the process, such as the effects of pad wear. The advantage of dry in-line metrology is that the index of refraction difference between the top oxide layer and the air is much greater than that between water and the oxide, and consequently the signal-to-noise ratio is larger than is the case with wet measurements.
Figure 18 shows  a plot of the spectral reflectance of a SO,-TiN-A1 film stack in air and in water. It is clear that the spectral signature in both cases lends itself to determining the oxide thickness, but that the amplitude of the oscillations is considerably less in the case of measurements made in water than those made in air. Also, they use no DI water, so there is no additional ongoing cost.
The point is that both approaches can work. Nova manufactures a wet system  and is responsible for creating the market for in-line metrology tools for CMP. Nanometri produces a dry wafer measurement system. Run-to-run control systems using integrated metrology are beginning to exploit the potential of in-line measurements . For proper control, both pre- and postmeasurements must be made.
With rising throughput requirements on CMP tools, the necessity of measuring wafers twice per wafer pass imposes stringent requirements on in-line metrology tools. They include optical, electrical, and acoustic sensing. Given the benefits of EPD, it is no surprise that many of these methods have been awarded patents. Some of these methods, most notably current sensing, have been developed to become commercially viable products while others remain laboratory curiosities.
For a review of in situ endpoint detection methods up to early , see the work of Bibby and Holland . Within the latter two categories fall a variety of slurries depending on the specific material being polished.
The chemistry and related issues are discussed elsewhere in this book. There are, however, a couple of points related to slurry that bear on CMP tool performance. Unlike other parts of semiconductor wafer processing, the cost of consumables used in CMP is a significant cost to the end user. Consider the following example in which one wishes to remove 12, Aof oxide. It would also produce approximately 27, gal of waste slurry that requires treatment at additional cost.
Reducing slurry consumption has been achieved by increasing the efficiency with which slurry is used. This has been achieved using direct slurry deliver systems in which slurry use is cut in half. Alternatively, reusing or reprocessing slurry has been proposed .
Such reprocessing systems actually improve the quality of the process because the slurry pH is adjusted to maintain peak performance. Although such systems offer potentially huge savings, they have not experienced market acceptance in spite of pleas from manufacturers for further development . Copper Polishing and CMP Tool Requirements There are areas in which equipment advances are being made that will enable greater flexibility in processing.
Such advances are particularly important as advanced interconnection concepts are implemented. In particular, copper CMP is evolving rapidly. Although tantalum is widely used as a barrier metal for Cu damascene, TaN, WN, and CoWP have also been reported for use in copper interconnection technologies. High barrier-layerremoval rates are essential to minimize metal dishing and dielectric erosion.
It is also necessary to obtain high selectivity to underlying dielectrics to reduce dielectric erosion values and to minimize dielectric loss in field areas. To achieve high barrier-removal-rates without increasing Cu dishing it may be necessary to rapidly change the slurry when the bulk copper is cleared. Thus reliable and consistent endpoint technology will be necessary. Optical endpoint technology, such as the broadband optical endpoint system that produced the endpoint trace shown in Fig. Depending on the ability of slurry suppliers to develop slurries capable of removing both copper and barrier layers without excessive dishing, it may be necessary to use multiple slurries, and possibly to polish wafers on more than one head.
The point here is that flexibility is key. It is important that customers have the capability of delivering different slurries to a given head within a polish cycle and to different heads within a tool if desired. In addition to controlling the standard process parameters such as down force and the relative velocity, it is also important to have random access capability to route wafers through a CMP tool to optimize both performance and throughput. Low-down-force processes and special CMP pads are likely to be necessary to reduce copper dishing just as they improve oxide planarization.
Furthermore, a balance between high relative velocity to reduce copper dishing and moderate relative velocity to minimize the sheering of small oxide feature may be necessary. Endpoint signal from a copper CMP process. With the growing level of control of copper CMP process comes the requirement for temperature control.
Copper CMP is highly temperature sensitive, so hot slurry will enhance the removal of bulk copper. However, barrier metals are significantly less reactive with the slurries currently available , so there is a significantly greater mechanical contribution to the removal of the barrier layer s. Consequently, hot slurry is of little benefit for barrier layer removal and may soften the pad and aggravate metal dishing and dielectric erosion. Key performance issues include metal thinning and dielectric erosion.
To minimize metal thinning and dielectric erosion it is advantageous to use a hard pad. An option on some tools is the capability of switching from one pad to another, and in some circumstances this is the best route. However, doing so can lead to a reduction in throughput, even in the presence of random wafer access capability. By being able to quickly cool the slurry, the process can be converted to a largely mechanical one using a relatively stiff pad. Figure 20 shows the benefit of multiple process steps on metal thinning and dielectric erosion.
In the future, pH control will also be a desirable capability. This capability already exists with tools on which slurries can be changed quickly and may be particularly useful with secondary slurries designed for specific barrier layers or for buffing. Benefit of using a multistep CMP processes on a n orbital tool using slurry delivered directly to the surface of the wafer. Some work has already been done on reprocessing slurry, but to date the focus has been on oxide slurry reprocessing. Given the remarkably high contribution of slurry cost to the overall cost of ownership, one can reasonably expect that slurry reprocessing will play a greater role in the future.
Since IC manufacturers and capital equipment suppliers began to develop mm-based fabs and equipment, the startup date of mm-wafer-based IC manufacturing set out in the Semiconductor Industry Association SIA road map  of has varied by several months to several years. These variations in estimated startup dates are due to fluctuations in the economic climate coupled with very successful die shrinkage, and are due in part to the successful implementation of CMP. The economic slowdown of has cut into the available funds for process development, both of mm-capable CMP tools and also of the other semiconductor processing tools.
The availability of thin film deposition equipment capable of processing mm wafers has also been limited, but this improved significantly since mm development work began. Furthermore, the means of evaluating either deposited or planarized thin films has been affected by the limited availability of mm-capable metrology tools. At the beginning of , there were only lab-based metrology tools; in , several manufacturers are offering mm-capable tools.
The result has been process development that consists of wafers being sent from lab to lab at each step of the process. Thus, process development has been slow. An additional factor contributing to the modest pace of development are the high cost of wafers. One factor that is different from earlier transitions is the increased reliance IC manufacturers are placing on the capital equipment vendors to share some of the burden of the development costs associated with the transition to mm wafers. Although this shift is complementary to the maturing capabilities of the equipment vendors, it is placing enormous strain on them.
Few vendors are in a position to provide new tools, engineering support, and process support in multiple sites for upward of a year with only the promise of remaining in contention for the substantial capital equipment purchases that can justify such significant investment of resources. Conclusion There has been dramatic improvement in the capabilities of CMP tools in the s. Early limitations of low throughput and the high cost of consumables has driven suppliers to make significant improvements, especially in the area of throughput and process quality. Even with the dramatic increase in activity in developing copper C M P processes, the anticipated work in low k dielectric CMP has not changed the focus of effort.
Ironically, the ongoing drive for ever improving processes has caused the focus of effort in tool design to remain essentially the same. Emphasis in CMP technology in has evolved from a nearly exclusive focus on traditional polish systems to the use in manufacturing of advanced second- and third-generation polishers. The development of slurry reprocessing for oxide CMP, and the introduction to the market of integrated metrology for CMP by nearly all of the equipment suppliers is expected to have a significant impact on CMP cost of ownership.
This broad range of developments indicates that CMP is becoming an integrated process in semiconductor manufacturing facilities with a diverse arsenal of supporting tools. CMP is an enabling technology for the less than 0. The future of CMP is very bright, and the technology is poised for dramatic developments in the months and years to come. Kaanta, W. Cote, J. Cronin, K. Holland, P. Lee, T. Meeting Technical Digest, pp. Pennington, S. Murarka, R. Holland, T. Price, R. Gutmann, S. Thin Solid Films, , pp.
Wang, C. Liu, M. Feng, J. Dun, K. Andricacos, C. Uzoh, J. Dukovic, J. Horkans, H. Bibby, J. Adams, K. Holland, G. Krulik, P. Jairath, A. Pant, T. Mallon, B. Withers, W. Withers, E. Zhoa, R. Shendon, D. Smith, US. Patent 5,,, Dec. Bibby, A. Zutshi, Y. Gotkis, J.
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